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Proceedings Paper

Crossing the divide between lithography and chip design
Author(s): William H. Arnold; J. Fung Chen; Kurt E. Wampler
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Paper Abstract

0.7X reduction every two years, as required by Moore's Law, has increased the emphasis on low k1 imaging. Low k1 is a way to extend each wavelength one node. However, with low k1 imaging, a significant divide opens between the desires of the chip designer and the realities of lithographic reproduction. As k1 decreases from the safe and comfortable 0.8 value enjoyed in the 1980s, to the more stringent 0.5 adopted in production in the 90s, lithographers had to beg designers to let them do line biasing and place hammerheads at the ends of gates in order to compensate for simple proximity effects like iso-dense bias and line end shortening. Now, in the new millenium, many chip makers have to develop processes that work below 0.4 k1, which brings new tensions between the designer and the lithographer in the forms of design rule restrictions, 2D OPC, forbidden pitches, phase assignments, double exposure decompositions, etc.

Paper Details

Date Published: 12 July 2002
PDF: 11 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475661
Show Author Affiliations
William H. Arnold, ASML TDC (United States)
J. Fung Chen, ASML Masktools, Inc. (United States)
Kurt E. Wampler, ASML Masktools, Inc. (United States)


Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Kenneth W. Tobin; Alexander Starikov, Editor(s)

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