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Proceedings Paper

Defect detection for short-loop process and SRAM-cell optimization by using addressable failure site-test structures (AFS-TS)
Author(s): Kelvin Yih-Yuh Doong; Sunnys Hsieh; S. C. Lin; J. R. Wang; Binson Shen; L. J. Hung; J. C. Guo; I. C. Chen; K. L. Young; Charles Ching-Hsiang Hsu
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Paper Abstract

This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Paper Details

Date Published: 12 July 2002
PDF: 7 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475644
Show Author Affiliations
Kelvin Yih-Yuh Doong, Taiwan Semiconductor Manufacturing Co., Ltd. and National Tsing-Hua Univ. (Taiwan)
Sunnys Hsieh, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
S. C. Lin, Taiwan Semiconductor Manufacturing Corp., Ltd. (Taiwan)
J. R. Wang, National Tsing-Hua Univ. (China)
Binson Shen, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
L. J. Hung, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
J. C. Guo, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
I. C. Chen, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
K. L. Young, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Charles Ching-Hsiang Hsu, National Tsing-Hua Univ. (Taiwan)


Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Kenneth W. Tobin; Alexander Starikov, Editor(s)

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