Share Email Print
cover

Proceedings Paper

Novel scheme for a higher bandwidth sensor readout
Author(s): Ashok Srivastava; Harish N. Venkata; Pratul K. Ajmera
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Circuit design for a novel scheme for converting a multiple- valued output voltage forma sensor into a binary-coded output for signal processing is described here. Floating gate MOSFETs and floating gate potential diagrams have been used to design a readout integrated circuit in a standard 1.5 micrometers digital CMOS VLSI technology. The physical design is simulated and tested with SPICE using MOSIS BSIM3 MOS model parameters. Initial results on fabricated devices for the conversion of quaternary input into binary output have shown agreement with the corresponding simulated values. The method is simple and compatible with current CMOS processes. The circuit can be integrated with output of a sensor fabricated in MEMS-CMOS technology.

Paper Details

Date Published: 11 July 2002
PDF: 12 pages
Proc. SPIE 4700, Smart Structures and Materials 2002: Smart Electronics, MEMS, and Nanotechnology, (11 July 2002); doi: 10.1117/12.475050
Show Author Affiliations
Ashok Srivastava, Louisiana State Univ. (United States)
Harish N. Venkata, Louisiana State Univ. (United States)
Pratul K. Ajmera, Louisiana State Univ. (United States)


Published in SPIE Proceedings Vol. 4700:
Smart Structures and Materials 2002: Smart Electronics, MEMS, and Nanotechnology
Vijay K. Varadan, Editor(s)

© SPIE. Terms of Use
Back to Top