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Proceedings Paper

OPC applications into embedded-OPC designs
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Paper Abstract

To achieve the demand of the ever-shrinking technologies, design engineers are embedding rule-based OPC (Optical Proximity Correction) or hand-applied OPC into bit-cell libraries. These libraries are then used to generate other components on a chip. This creates problems for the end users, the photolithographers. Should the photolithographer change the process used to generate the simulations for the embedded OPC, the process can become unstable. The temptation to optimize these shrinking cells with embedded adjustments can be overcome by other methods. Manually increasing fragmentation or manually freezing portions of bit cells can provide the same level of accuracy as a well-simulated embedded solution, so now the model-base OPC generated by the end user can be applied, tolerating process or illumination changes. Manually freezing portions of a bit cell can assist in optimization by blocking larger features from receiving a model-based solution, whereas increased fragmentation augments the model-based application. Freezing contacts or local interconnects landing sites at poly for example, would allow the model-based OPC to optimize the poly over the active regions where transistor performance is vital. This paper documents the problems seen with embedding OPC and the proper ways to resolve them. It will provide insight into embedded OPC removal and replacement. Simulations and empirical data document the differences seen between embedded-OPC bit cells and fragment-optimized bit cells.

Paper Details

Date Published: 30 July 2002
PDF: 10 pages
Proc. SPIE 4691, Optical Microlithography XV, (30 July 2002); doi: 10.1117/12.474502
Show Author Affiliations
George E. Bailey, LSI Logic Corp. (United States)
Travis E. Brist, LSI Logic Corp. (United States)


Published in SPIE Proceedings Vol. 4691:
Optical Microlithography XV
Anthony Yen, Editor(s)

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