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Proceedings Paper

Overlay accuracy in 0.18-micron copper dual-damascene process
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Paper Abstract

As overlay budgets shrink with design rules, the importance of overlay metrology accuracy increases. We have investigated the overlay accuracy of a 0.18mm design rule Copper-Dual-Damascene process by comparing the overlay metrology results at the After Develop (DI) and After Etch (FI) stages. The comparisons were done on five process layers on production wafers, while ensuring that the DI and FI measurements were always done on the same wafer. In addition, we measured the in-die overlay on one of the process layers (Poly Gate) using a CD-SEM, and compared the results to the optical overlay metrology in the scribe-line. We found that a serious limitation to in-die overlay calibration was the lack of suitable structures measurable by CD-SEM. We will present quantitative results from our comparisons, as well as a recommendation for incorporating CD-SEM-measurable structures in the chip area in future reticle designs.

Paper Details

Date Published: 16 July 2002
PDF: 11 pages
Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); doi: 10.1117/12.473477
Show Author Affiliations
Bernd Schulz, AMD Saxony Manufacturing GmbH (Germany)
Harry J. Levinson, Advanced Micro Devices, Inc. (United States)
Rolf Seltmann, AMD Saxony Manufacturing GmbH (Germany)
Joel L. Seligson, KLA-Tencor Corp. (Israel)
Pavel Izikson, KLA-Tencor Corp. (Israel)
Anat Ronen, KLA-Tencor Corp. (Israel)


Published in SPIE Proceedings Vol. 4689:
Metrology, Inspection, and Process Control for Microlithography XVI
Daniel J. C. Herr, Editor(s)

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