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Proceedings Paper

Ultrafast wafer alignment simulation based on thin film theory
Author(s): Qiang Wu; Gary Williams; Byeong Y. Kim; Jay Strane; Timothy J. Wiltshire; Eric A. Lehner; Hiroyuki Akatsu
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Paper Abstract

The shrink of semiconductor fabrication ground rule continues to follow Moore's law over the past years. However, at the 100 nm node, the fabrication cost starts to rise rapidly. This is mainly due tot he increase of complexity in the fabrication process, including the use of hard masks, planarization, resolution enhancement techniques, etc. Smaller device sizes require higher alignment tolerances. Also, higher degree of complexity makes alignment detection more difficult. For example, planarization techniques may destroy mark topography; hard masks may optically bury alignment marks, and more film layers makes the alignment signal more susceptible to process variations. Therefore in order to achieve reliable alignment, it is absolutely critical to develop an accurate and fast simulation software that can characterize alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment signal simulator for both direct imaging and diffractive detection system based on simple optical theory. We will demonstrate through examples using our advanced DRAM products that it is capable of accurately mapping the multi-dimensional parameter space spanned by various film thickness parameters within a short period of time, which allows both on-the-fly feedback in alignment performance and alignment optimization.

Paper Details

Date Published: 16 July 2002
PDF: 10 pages
Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); doi: 10.1117/12.473475
Show Author Affiliations
Qiang Wu, IBM Microelectronics Div. (United States)
Gary Williams, Infineon Technologies Corp. (United States)
Byeong Y. Kim, IBM Microelectronics Div. (United States)
Jay Strane, IBM Microelectronics Div. (United States)
Timothy J. Wiltshire, IBM Microelectronics Div. (United States)
Eric A. Lehner, IBM Microelectronics Div. (United States)
Hiroyuki Akatsu, IBM Microelectronics Div. (United States)


Published in SPIE Proceedings Vol. 4689:
Metrology, Inspection, and Process Control for Microlithography XVI
Daniel J. C. Herr, Editor(s)

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