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Proceedings Paper

Evaluation of ASML ATHENA alignment system on Intel front-end processes
Author(s): Graham M. Pugh; Maria Rebecca Giorgi
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Paper Abstract

An evaluation of the ASML ATHENA alignment system was performed using marks placed in the scribeline of an Intel test chip used for 130 nm node processing. Exposures were performed using two ASML scanners at IMEC at the isolation, gate, contact and first metal layers, with extreme process splits performed at Intel at critical steps in between. The splits were arranged as factorials in order to evaluate the process sensitivity of the alignment system. The modeled overlay terms with the largest sensitivities are discussed. In addition, data taken by the scanners on various mark/recipe combinations is analyzed to provide insight into overlay optimization and potential alignment system limitations.

Paper Details

Date Published: 16 July 2002
PDF: 9 pages
Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); doi: 10.1117/12.473468
Show Author Affiliations
Graham M. Pugh, Intel Corp. (Belgium)
Maria Rebecca Giorgi, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 4689:
Metrology, Inspection, and Process Control for Microlithography XVI
Daniel J. C. Herr, Editor(s)

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