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Proceedings Paper

Three-dimensional modeling of wafer inspection schemes for sub-70-nm lithography
Author(s): Zhengrong Zhu; Aaron L. Swecker; Andrzej J. Strojwas
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Paper Abstract

The production of 70nm devices is projected for the year 2008. With this projection, optical lithography will become more challenging since as the device size goes down, the potential for introducing killer defects also increases dramatically. Wafer inspection will play a key role in controlling the defect mechanisms and keeping an acceptable yield for next generation VLSI manufacturing. Metrology tools for the new generation lithography will have the following features. First, the projection and collection lenses will have higher numerical apertures (NA) to obtain high-resolution images. Typically, the NA will be as high as 0.9. Second, the wavelength used for wafer inspection will be much smaller so that common wafer materials will become highly absorptive. Last, with the increased number of process steps, wafer inspection will need to provide information for more critical processes. Based on these features, accurate modeling of the next generation wafer inspection schemes is needed to aid in the characterization and optimization of the inspection tools. The simulation tool must be able to simulate inspection systems with high NA lens, DUV wavelengths, and highly absorptive wafer materials accurately and quickly. At Carnegie Mellon University, a simulator called METRO-3D was developed into a defect inspection simulator for DUV lithography processes. This simulator is able to successfully model various types of defect mechanisms. However, it has experienced occasional numerical instabilities, with discontinuous dielectric structures composed of highly absorptive materials. In order to provide a tool to simulate the wafer inspection scheme of SUB-70NM NODE LITHOGRAPHY, we have incorporated a new algorithm to model the wafer inspection system more accurately and robustly. Numerical experiments shows that the algorithm is capable of simulating topographies with discontinuous dielectric functions, yielding stable results even when the material is highly absorptive. To verify the accuracy of the simulator, several simulations were compared with both analytical models and results form other existing simulators. The results show good matches between METRO-3D and these well-established results. Finally, we performed simulations on industrial data and the results exemplified the ability of METRO-3D to model complex 3-D structures. In this paper we will present is efficient and stable EM solver and the results of the simulator applied to various sub-70nm node wafer inspection schemes.

Paper Details

Date Published: 16 July 2002
PDF: 12 pages
Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); doi: 10.1117/12.473455
Show Author Affiliations
Zhengrong Zhu, Carnegie Mellon Univ. (United States)
Aaron L. Swecker, Carnegie Mellon Univ. (United States)
Andrzej J. Strojwas, Carnegie Mellon Univ. (United States)


Published in SPIE Proceedings Vol. 4689:
Metrology, Inspection, and Process Control for Microlithography XVI
Daniel J. C. Herr, Editor(s)

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