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Proceedings Paper

Improved characteristics of rainbow defects with novel wafer edge exposure technique
Author(s): Kew-Chan Shim; Myoung-Soo Kim; Eung-Sok Lee; Chang-Seong Lee; Chul-Seung Lee; Myung-Goon Gil; Bong-Ho Kim; Jae-Sig In; Tae Bong Yoon; Jai-soon Kim
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Paper Abstract

The demand for manufacturing integrated circuit with high circuit speed and high packing density requires reduced feature sizes in ULSI structures. As the device feature size shrinks below sub-130 nm it needs the tight control of defect reduction in lithography process. Especially, resist peeling at the wafer edge is one of the major sources for particle generation. The WEE process removes resist up to a width of a few mm from the wafer edge in order to prevent particle generation in succeeding process. The defect induced form wafer edge after WEE has given the critical damage to electrical properties and device yield. In this paper, we have applied novel WEE kit to reduce the rainbow bandwidth caused by WEE step in wafer wedge. The novel WEE kit consists of chrome slit and lens assembly to minimize the scattering of UV beam from the optic fiber in comparison with the conventional WEE kit. The change of rainbow bandwidth was also characterized by OM and SEM. With the novel WEE kit the bandwidth of rainbow is reduced to 5 micrometers , while the conventional WEE kit has been induced 20 micrometers of bandwidth on bare silicon wafer. In the case of patterned wafer, the bandwidth of rainbow is reduced to 60 micrometers for the novel WEE kit, while the conventional WEE kit has induced 230 micrometers of bandwidth. Therefore, ti is confirmed that the application of novel WEE kit has induced 230 micrometers of bandwidth. Therefore, it is confirmed that the application of novel WEE kit for patterned process makes less rainbow defect and finally increases the device yield for mass production.

Paper Details

Date Published: 16 July 2002
PDF: 8 pages
Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); doi: 10.1117/12.473420
Show Author Affiliations
Kew-Chan Shim, Hynix Semiconductor Inc. (South Korea)
Myoung-Soo Kim, Hynix Semiconductor Inc. (South Korea)
Eung-Sok Lee, Hynix Semiconductor Inc. (Japan)
Chang-Seong Lee, Hynix Semiconductor Inc. (South Korea)
Chul-Seung Lee, Hynix Semiconductor Inc. (South Korea)
Myung-Goon Gil, Hynix Semiconductor Inc. (South Korea)
Bong-Ho Kim, Hynix Semiconductor Inc. (South Korea)
Jae-Sig In, NARAE Technology Inc. (South Korea)
Tae Bong Yoon, NARAE Technology Inc. (South Korea)
Jai-soon Kim, NARAE Technology Inc. (Japan)


Published in SPIE Proceedings Vol. 4689:
Metrology, Inspection, and Process Control for Microlithography XVI
Daniel J. C. Herr, Editor(s)

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