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Proceedings Paper

Wafer thinning for high-density through-wafer interconnects
Author(s): Lianwei Wang; Cassan C. G. Visser; Charles R. de Boer; M. Laros; W. van der Vlist; J. Groeneweg; G. Craciun; Pasqualina M. Sarro
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Paper Abstract

Thinning of micromachined wafers containing trenches and cavities to realize through-chip interconnects is presented. Successful thinning of wafers by lapping and polishing until the cavities previously etched by deep reactive ion etching are reached is demonstrated. The possible causes of damage to the etched structures are investigated. The trapping of particles in the cavities and suitable cleaning procedures to address this issue are studied. The results achieved so far allow further processing of the thinned wafers to form through wafer interconnections by copper electroplating. Further improvement of the quality of thinned surfaces can be achieved by alternative cleaning procedures.

Paper Details

Date Published: 15 January 2003
PDF: 8 pages
Proc. SPIE 4979, Micromachining and Microfabrication Process Technology VIII, (15 January 2003); doi: 10.1117/12.473374
Show Author Affiliations
Lianwei Wang, Delft Univ. of Technology (Netherlands)
Cassan C. G. Visser, Delft Univ. of Technology (Netherlands)
Charles R. de Boer, Delft Univ. of Technology (Netherlands)
M. Laros, Delft Univ. of Technology (Netherlands)
W. van der Vlist, Delft Univ. of Technology (Netherlands)
J. Groeneweg, Delft Univ. of Technology (Netherlands)
G. Craciun, Delft Univ. of Technology (Netherlands)
Pasqualina M. Sarro, Delft Univ. of Technology (Netherlands)


Published in SPIE Proceedings Vol. 4979:
Micromachining and Microfabrication Process Technology VIII
John A. Yasaitis; Mary Ann Perez-Maher; Jean Michel Karam, Editor(s)

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