Share Email Print

Proceedings Paper

Low-power serial-parallel bootstrapped dynamic shift register
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In this paper a new low power area efficient serial-to-parallel shift register design is presented. The design of the register only contains 4 transistors per stage and uses a capacitive bootstrapping technique to offset the threshold voltage drop of MOSFETs. We shall refer to this logic family as Non-Ratioed Bootstrap Logic (NRBL). The intended target applications are in smart sensor arrays and image sensors for use in the select registers to control the photo diode array.

Paper Details

Date Published: 14 November 2002
PDF: 9 pages
Proc. SPIE 4935, Smart Structures, Devices, and Systems, (14 November 2002); doi: 10.1117/12.472851
Show Author Affiliations
Leo Lee, Univ. of Adelaide (Australia)
Said F. Al-Sarawi, Univ. of Adelaide (Australia)
Derek Abbott, Univ. of Adelaide (Australia)

Published in SPIE Proceedings Vol. 4935:
Smart Structures, Devices, and Systems
Erol C. Harvey; Derek Abbott; Vijay K. Varadan, Editor(s)

© SPIE. Terms of Use
Back to Top