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Proceedings Paper

Planarization of a CMOS die for an integrated metal MEMS
Author(s): Hocheol Lee; Michele H. Miller; Thomas G. Bifano
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Paper Abstract

This paper describes a planarization procedure to achieve a flat CMOS die surface for the integration of a MEMS metal mirror array. The CMOS die for our device is 4 mm × 4 mm and comes from a commercial foundry. The initial surface topography has 0.9 μm bumps from the aluminum interconnect patterns that are used for addressing the individual micro mirror array elements. To overcome the tendency for tilt error in the planarization of the small CMOS die, our approach is to sputter a thick layer of silicon nitride (2.2 μm) at low temperature and to surround the CMOS die with dummy pieces to define the polishing plane. The dummy pieces are first lapped down to the height of the CMOS die, and then all pieces are polished. This process reduces the 0.9 μm height of the bumps to less than 25 nm.

Paper Details

Date Published: 15 January 2003
PDF: 8 pages
Proc. SPIE 4979, Micromachining and Microfabrication Process Technology VIII, (15 January 2003); doi: 10.1117/12.472803
Show Author Affiliations
Hocheol Lee, Boston Univ. (United States)
Michele H. Miller, Boston Univ. (United States)
Thomas G. Bifano, Boston Univ. (United States)

Published in SPIE Proceedings Vol. 4979:
Micromachining and Microfabrication Process Technology VIII
John A. Yasaitis; Mary Ann Perez-Maher; Jean Michel Karam, Editor(s)

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