Share Email Print
cover

Proceedings Paper

Dynamic image placement accuracy of a stencil mask
Author(s): Hiroshi Takenaka; Hiroshi Yamashita; Kimitoshi Takahashi; Yoichi Tomo; Manabu Watanabe; Teruo Iwasaki; J. Yamamoto; Masaki Yamabe
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Stencil masks are preferable for EPL (Electron-beam Projection Lithography)from the view point of resolution because it 's free from the chromatic aberration caused by the electron energy loss in continuous membrane. However, its mechanical structure poses several concerns. Dynamic image placement (IP)accuracy is one of the essential concerns because patterns on the stencil mask are defined by free-standing Si structures. Moreover the whole pattern areas are supported by fine Si grid structures. The step-and-scan motion of EPL tools is expected to cause dynamic displacements of these fragile structures, which lead to deterioration of resolution, critical dimension (CD)and overlay (OL) accuracies. Two kinds of the dynamic displacements on an EPL stencil mask were estimated by simulations. One is the vibration of the free-standing structures and the other is the dynamic distortion of the whole pattern area. The maximum acceleration of 5 G was assumed in the simulations according to a throughput estimation. The free-standing structures are modeled into cantilever beams and both-end-fixed beams. It was found that the vibration of the structures could be suppressed below the amplitude of 1 nm by limiting the beam length. The limitations were practical ones for complementary split of mask layout. The whole pattern area was modeled into a simple grid structure. It was found that the maximum dynamic displacement was less than 7 nm. The OL accuracy was estimated including those dynamic displacements down to 35 nm node. The results show that the dynamic displacements of the EPL stencil masks would little affect the OL accuracy. The stencil mask is applicable for device fabrication at 70 nm node and below.

Paper Details

Date Published: 1 July 2002
PDF: 11 pages
Proc. SPIE 4688, Emerging Lithographic Technologies VI, (1 July 2002); doi: 10.1117/12.472269
Show Author Affiliations
Hiroshi Takenaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroshi Yamashita, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kimitoshi Takahashi, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yoichi Tomo, Semiconductor Leading Edge Technologies, Inc. (Japan)
Manabu Watanabe, Semiconductor Leading Edge Technologies, Inc. (Japan)
Teruo Iwasaki, Semiconductor Leading Edge Technologies, Inc. (Japan)
J. Yamamoto, Semiconductor Leading Edge Technologies, Inc. (Japan)
Masaki Yamabe, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 4688:
Emerging Lithographic Technologies VI
Roxann L. Engelstad, Editor(s)

© SPIE. Terms of Use
Back to Top