Share Email Print
cover

Proceedings Paper

Emerging technologies for chip-level optical interconnects
Author(s): Serge Oktyabrsky; James Castracane; Alain E. Kaloyeros
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Interconnect bottleneck in emerging integrated circuitry (IC) has generated a need for alternative signal transmission solutions, such as optical technologies, in chip-level applications. The present paper discusses target parameters for chip-level optical interconnects (CLOIs) that yield superior performance starting with the 70 nm IC node, and possibly extending down to the 25-15 nm node. The benefits and disadvantages of various CLOI system and component solutions are reviewed. In particular, this paper discusses critical fundamental and technological challenges that need resolution to enable massively parallel CLOI links with a total throughput of 10-25 Tb/s, reduced power consumption in comparison with electrical wires, and enhanced density. Recent results from the presenting authors are summarized with an emphasis on CLOI specific solutions. These results include the development of InAs quantum dot gain medium to increase the operating temperature of laser arrays above that of Si ICs. Controllable routing of VCSEL- emitted beams is carried out through a microsystem-based reconfigurable free-space interconnect system which employs optical diffractive or reflective structures. This work also explores a novel hybrid integration protocol that allows self-aligned bonding of massive arrays of III-V components to Si electronics, and ensures low thermal budget and reduced stress.

Paper Details

Date Published: 3 June 2002
PDF: 12 pages
Proc. SPIE 4652, Optoelectronic Interconnects, Integrated Circuits, and Packaging, (3 June 2002); doi: 10.1117/12.469568
Show Author Affiliations
Serge Oktyabrsky, SUNY/Albany (United States)
James Castracane, SUNY/Albany (United States)
Alain E. Kaloyeros, SUNY/Albany (United States)


Published in SPIE Proceedings Vol. 4652:
Optoelectronic Interconnects, Integrated Circuits, and Packaging
Louay A. Eldada; Randy A. Heyler; John R. Rowlette; John R. Rowlette; Randy A. Heyler, Editor(s)

© SPIE. Terms of Use
Back to Top