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Proceedings Paper

Flexible mask specifications
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Paper Abstract

As feature sizes of semiconductor devices shrink, mask errors have a large impact on critical dimension (CD) variation on a wafer and lead to lithography margin reduction. Observed CD error on a wafer is 2 to 4 times as large as CD error on a mask under the low k1 lithography due to mask CD deviation enhancement factor. Mask errors, e.g. CD uniformity, mean to target error, should be controlled and assessed to prevent CD variation on a wafer and lithography margin reduction. Therefore, assessment of mask quality is a critical step in mask manufacturing. This paper proposes a methodology for assessment of mask quality, flexible mask specifications. The methodology consists of two major concepts. One is flexibly selected patterns to guarantee mask quality for each device and each level of devices using full-chip level lithography simulation. The other is flexibly changeable combination of each tolerance for each error component. The validity of flexible mask specifications is proved on masks of a 130nm node memory device. Using the flexible mask specifications, we have confirmed that mask-manufacturing yield rises by 20% for masks of a 175nm node memory device compared with the yield of the masks judged by conventional mask specifications.

Paper Details

Date Published: 27 December 2002
PDF: 10 pages
Proc. SPIE 4889, 22nd Annual BACUS Symposium on Photomask Technology, (27 December 2002); doi: 10.1117/12.469361
Show Author Affiliations
Shigeki Nojima, Toshiba Corp. (Japan)
Shoji Mimotogi, Toshiba Corp. (Japan)
Masamitsu Itoh, Toshiba Corp. (Japan)
Osamu Ikenaga, Toshiba Corp. (Japan)
Shigeru Hasebe, Toshiba Corp. (Japan)
Kohji Hashimoto, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)
Mineo Goto, Toshiba Corp. (Japan)
Ichiro Mori, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 4889:
22nd Annual BACUS Symposium on Photomask Technology
Brian J. Grenon; Kurt R. Kimmel, Editor(s)

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