Share Email Print

Proceedings Paper

Optimization of side gate length and side gate voltage for sub-100-nm double-gate MOSFET
Author(s): Jae-hong Kim; Geun-ho Kim; Suk-woong Ko; Hak-kee Jung
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (MG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 2V in the main gate 50nm. Also, we know that optimum side gate length for each main gate length is 70nm above. DG MOSFET shows a small threshold voltage (Vth) roll-off. From the I-V characteristics, we obtained IDsat=510μA/μm at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86mV/decade, transconductance is 111μA/V and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Also, we have presented that TCAD simulator is suitable for device simulation.

Paper Details

Date Published: 14 November 2002
PDF: 8 pages
Proc. SPIE 4935, Smart Structures, Devices, and Systems, (14 November 2002); doi: 10.1117/12.469072
Show Author Affiliations
Jae-hong Kim, Kunsan National Univ. (South Korea)
Geun-ho Kim, Kunsan National Univ. (South Korea)
Suk-woong Ko, Kunsan National Univ. (South Korea)
Hak-kee Jung, Kunsan National Univ. (South Korea)

Published in SPIE Proceedings Vol. 4935:
Smart Structures, Devices, and Systems
Erol C. Harvey; Derek Abbott; Vijay K. Varadan, Editor(s)

© SPIE. Terms of Use
Back to Top