Share Email Print

Proceedings Paper

Investigation of the design boundaries of a 3,072 x 2,048 image sensor pixel array
Author(s): El-Sayed I. Eid
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The practical boundaries surrounding the design of very high resolution image sensors have been studied. The case study used to analyze these practical boundaries is a CMOS photodiode active pixel sensor (APS) image sensor with pixel array format of 3,072 (H) X 2,048 (V). The frame rate of the image sensor is variable up to 30 frames per second (fps), leading to a maximum image data throughput of 180 M pixels per second. The pixel size is 6.0 μm, resulting in a pixel fill factor of approximately 48% (implemented in a 0.25 μm CMOS fabrication process) and a 4/3 inch optical format. The resultant die fill factor is approximately 54%. The column-parallel approach, which works well for both the on-chip analog signal processing and analog-to-digital conversion, is adopted. The 10-bit successive approximation ADC was deemed suitable for on-chip integration. The projected total power consumption of the case study image sensor chip is below 200 mW at 3.3-V power supply and below 100 mW at 1.5-V power supply. These power estimates were made for operation at full resolution (6 M pixels per frame) and at maximum frame rate (30 fps), leading to a maximum digital image data throughput of 1.8 G bits per second.

Paper Details

Date Published: 11 November 2002
PDF: 9 pages
Proc. SPIE 4823, Photonics for Space Environments VIII, (11 November 2002); doi: 10.1117/12.465858
Show Author Affiliations
El-Sayed I. Eid, Gentex Corp. (United States)
Alexandria Univ. (Egypt)

Published in SPIE Proceedings Vol. 4823:
Photonics for Space Environments VIII
Edward W. Taylor, Editor(s)

© SPIE. Terms of Use
Back to Top