Share Email Print

Proceedings Paper

Effects of etching time and wafer miscut on the morphology of etched Si(111) surfaces
Author(s): Hui Zhou; Joseph Fu; Sotoshi Gonda; Richard M. Silver
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Critical dimension metrology of silicon integrated circuit features at the sub-micrometer scale is an essential task in state-of-the-art semiconductor manufacturing. Determining the width of a feature or the scale in a pitch measurement with appropriate accuracy is consistently one of the most challenging elements of semiconductor metrology and manufacturing.

Paper Details

Date Published: 24 July 2002
PDF: 8 pages
Proc. SPIE 4608, Nanostructure Science, Metrology, and Technology, (24 July 2002); doi: 10.1117/12.465124
Show Author Affiliations

Published in SPIE Proceedings Vol. 4608:
Nanostructure Science, Metrology, and Technology
Martin C. Peckerar; Michael T. Postek Jr., Editor(s)

© SPIE. Terms of Use
Back to Top