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Proceedings Paper

On-chip binary image processing with CMOS image sensors
Author(s): Canaan Sungkuk Hong; Richard I. Hornsey
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Paper Abstract

In this paper, we demonstrate a CMOS active pixel sensor chip, integrated with binary image processing on a single monolithic chip. A prototype chip comprising a 64 X 64 photodiode array with on-chip binary image processing is fabricated in standard 0.35 micrometers CMOS technology, with 3.3 V power supply. The binary image processing functionality is embedded in the column structure, were each processing element is placed per column, reducing processing time and power consumption. This column processing structure is scalable to higher resolution. A 3 X 3 local mask (also called structure element) is implemented every column so that row-parallel processing can be achieved with a conventional progressive scanning method.

Paper Details

Date Published: 24 April 2002
PDF: 12 pages
Proc. SPIE 4669, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications III, (24 April 2002); doi: 10.1117/12.463419
Show Author Affiliations
Canaan Sungkuk Hong, Univ. of Waterloo (United States)
Richard I. Hornsey, Univ. of Waterloo (Canada)


Published in SPIE Proceedings Vol. 4669:
Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications III
Nitin Sampat; John Canosa; Morley M. Blouke; John Canosa; Nitin Sampat, Editor(s)

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