Share Email Print

Proceedings Paper

Miniaturized low-power parallel processor for space applications
Author(s): William J. Jacobi; Preben D. Jensen; Nicholas J. Teneketges; Leo A. Wadsworth
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

A miniaturized, low-power parallel processor for space applications is under development by Space Computer Corporation for DARPA's Advanced Space Technology Program. The basic goal of this project is the reduction, by an order of magnitude or more, of on-board processor weight, size, and power consumption for space-based sensor systems. The approach described here for achieving this goal is to use low-power VLSI devices which maximize throughput per watt, together with three-dimensional hybrid wafer-scale integration and packaging technology. In its prototype version, a 12-node processor will have a peak throughput greater than 1.2 GFLOPS and occupy a volume less than 15 cubic inches.

Paper Details

Date Published: 1 July 1991
PDF: 9 pages
Proc. SPIE 1495, Small-Satellite Technology and Applications, (1 July 1991); doi: 10.1117/12.45892
Show Author Affiliations
William J. Jacobi, Space Computer Corp. (United States)
Preben D. Jensen, Space Computer Corp. (United States)
Nicholas J. Teneketges, Space Computer Corp. (United States)
Leo A. Wadsworth, Space Computer Corp. (United States)

Published in SPIE Proceedings Vol. 1495:
Small-Satellite Technology and Applications
Brian J. Horais, Editor(s)

© SPIE. Terms of Use
Back to Top