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Proceedings Paper

Alternating phase shifting mask implementation to 0.1-um logic gates
Author(s): Chung-Hsing Chang; San-De Tzu; Chen-Hao Hsieh; Chang-Min Dai; Burn Jeng Lin; Chia-Hui Lin; Hua-Yu Liu
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Paper Abstract

Double exposure alternating phase-shift mask (alt-PSM) technology with ArF exposure was used in the 0.1 micrometers technology node for patterning logic devices with polysilicon gates ranging from 110nm to 60nm. A dual-trench mask fabrication process was developed in-house at TSMC, and controls for phase accuracy and intensity balance were established. Optical proximity correction (OPC) was performed on both binary masks and alt-PSM. Interactions between the binary and the PSM exposures were taking in to accounted during the correction. Using Model based OPC and a single calibrated resist model, the critical dimensions (CD) linearity can be ideally matched to the designed CD for duty ratio >= 1:1.5 for polygate logic product has been implemented exhibiting an enlarged DOF, good resist line edge roughness (LER), a d CD uniformity.

Paper Details

Date Published: 11 March 2002
PDF: 11 pages
Proc. SPIE 4562, 21st Annual BACUS Symposium on Photomask Technology, (11 March 2002); doi: 10.1117/12.458313
Show Author Affiliations
Chung-Hsing Chang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
San-De Tzu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Chen-Hao Hsieh, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Chang-Min Dai, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Burn Jeng Lin, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Chia-Hui Lin, Numerical Technologies, Inc. (Taiwan)
Hua-Yu Liu, Numerical Technologies, Inc. (United States)


Published in SPIE Proceedings Vol. 4562:
21st Annual BACUS Symposium on Photomask Technology
Giang T. Dao; Brian J. Grenon, Editor(s)

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