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Proceedings Paper

Integrated processor architecture for multisensor signal processing
Author(s): Robert E. Nasburg; Steve M. Stillman; M. T. Nguyen
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Paper Abstract

Sensor systems being conceived and fabricated today have high processor content and tend to be software intensive. Recent advances in hardware technology have made possible the implementation of complex high-performance multisensor algorithms. Hardware capability alone is not sufficient to ensure the successful implementation of these software intensive systems. In addition, it is necessary to carefully structure the processing system to ensure that high-performance multisensor algorithms can be implemented. Traditionally, implementability has meant throughput and memory capacity. This paper extends implementability to include the ability of a processing system architecture to support efficient integration and test. This is particularly important when the implicit requirements of cost and schedule are considered. To illustrate processor architecture impact on integration and test, an example from the LOWKATER program is examined. This was an extremely complex multisensor processor containing a digital laser radar receiver, a passive sensor target detector, and a digital controller for the beam pointing system. Architectural alternatives are presented and the selected architecture is examined in detail.

Paper Details

Date Published: 1 August 1991
PDF: 12 pages
Proc. SPIE 1481, Signal and Data Processing of Small Targets 1991, (1 August 1991); doi: 10.1117/12.45678
Show Author Affiliations
Robert E. Nasburg, Hughes Aircraft Co. (United States)
Steve M. Stillman, Hughes Aircraft Co. (United States)
M. T. Nguyen, Hughes Aircraft Co. (United States)

Published in SPIE Proceedings Vol. 1481:
Signal and Data Processing of Small Targets 1991
Oliver E. Drummond, Editor(s)

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