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Proceedings Paper

Minimizing energy dissipation of matrix multiplication kernel on Virtex-II
Author(s): Seonil Choi; Viktor K. Prasanna; Ju-wook Jang
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Paper Abstract

In this paper, we develop energy-efficient designs for matrix multiplication on FPGAs. To analyze the energy dissipation, we develop a high-level model using domain-specific modeling techniques. In this model, we identify architecture parameters that significantly affect the total energy (system-wide energy) dissipation. Then, we explore design trade-offs by varying these parameters to minimize the system-wide energy. For matrix multiplication, we consider a uniprocessor architecture and a linear array architecture to develop energy-efficient designs. For the uniprocessor architecture, the cache size is a parameter that affects the I/O complexity and the system-wide energy. For the linear array architecture, the amount of storage per processing element is a parameter affecting the system-wide energy. By using maximum amount of storage per processing element and minimum number of multipliers, we obtain a design that minimizes the system-wide energy. We develop several energy-efficient designs for matrix multiplication. For example, for 6×6 matrix multiplication, energy savings of upto 52% for the uniprocessor architecture and 36% for the linear arrary architecture is achieved over an optimized library for Virtex-II FPGA from Xilinx.

Paper Details

Date Published: 2 July 2002
PDF: 9 pages
Proc. SPIE 4867, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV, (2 July 2002); doi: 10.1117/12.455487
Show Author Affiliations
Seonil Choi, Univ. of Southern California (United States)
Viktor K. Prasanna, Univ. of Southern California (United States)
Ju-wook Jang, Sogang Univ. (South Korea)


Published in SPIE Proceedings Vol. 4867:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV
John Schewel; Philip B. James-Roxby; Herman H. Schmit; John T. McHenry, Editor(s)

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