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Proceedings Paper

Packed arithmetic on a prefix adder (PAPA)
Author(s): Neil Burgess
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Paper Abstract

This paper describes a new method for performing packed arithmetic on a prefix adder that enables sub-wordlength additions and subtractions to be performed in parallel on any prefix adder topology. A major benefit of the proposed technique is that the critical path length of the prefix carry tree is unaltered when measured as the number of complex CMOS logic gates. Moreover, there is no restriction on the prefix tree's cell topology and the adder is also capable of performing packed absolute difference and packed rounded average calculations.

Paper Details

Date Published: 6 December 2002
PDF: 10 pages
Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.453812
Show Author Affiliations
Neil Burgess, Cardiff Univ. (United Kingdom)


Published in SPIE Proceedings Vol. 4791:
Advanced Signal Processing Algorithms, Architectures, and Implementations XII
Franklin T. Luk, Editor(s)

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