Share Email Print
cover

Proceedings Paper

Study of thread-level parallelism in a video encoding application for chip multiprocessor design
Author(s): Eric Debes; Greg Kaine
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In media applications there is a high level of available thread level parallelism (TLP). In this paper we study the intra TLP in a video encoder. We show that a well-distributed highly optimized encoder running on a symmetric multiprocessor (SMP) system can run 3.2 faster on a 4-way SMP machine than on a single processor. The multithreaded encoder running on an SMP system is then used to understand the requirements of a chip multiprocessor (CMP) architecture, which is one possible architectural direction to better exploit TLP. In the framework of this study, we use a software approach to evaluate the dataflow between processors for the video encoder running on an SMP system. An estimation of the dataflow is done with L2 cache miss event counters using Intel® VTuneTM performance analyzer. The experimental measurements are compared to theoretical results.

Paper Details

Date Published: 21 November 2002
PDF: 8 pages
Proc. SPIE 4790, Applications of Digital Image Processing XXV, (21 November 2002); doi: 10.1117/12.452439
Show Author Affiliations
Eric Debes, Intel Corp. (United States)
Greg Kaine, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 4790:
Applications of Digital Image Processing XXV
Andrew G. Tescher, Editor(s)

© SPIE. Terms of Use
Back to Top