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Proceedings Paper

Design of a hybrid prefix adder for nonuniform input arrival times
Author(s): Youngmoon Choi; Earl E. Swartzlander
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Paper Abstract

This paper examines the design of a hybrid prefix adder under the condition of non-uniform input signal arrival. This is encountered in the final adder for fast parallel multipliers, which use column compression reduction. The prefix graph scheme efficiently accommodates the non-uniform arrival times. Rules are presented for designing hybrid prefix adders under such conditions. This rule produces adders which are faster and less complex than previous work.

Paper Details

Date Published: 6 December 2002
PDF: 10 pages
Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.452040
Show Author Affiliations
Youngmoon Choi, Univ. of Texas/Austin (United States)
Earl E. Swartzlander, Univ. of Texas/Austin (United States)


Published in SPIE Proceedings Vol. 4791:
Advanced Signal Processing Algorithms, Architectures, and Implementations XII
Franklin T. Luk, Editor(s)

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