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Proceedings Paper

Low-power array multiplier design by topology optimization
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Paper Abstract

Left-to-right (L-R) linear array multiplication provides an interesting alternative to the conventional right-to-left (R-L) array multiplication as L-R computation has the potential of saving power and delay. This paper presents topology optimization techniques for low-power L-R array multipliers. These techniques include: interconnect reorganization, addition modules other than 3-to-2 carry save adders for PP reduction, and split array architectures. Our experiments indicate that interconnect reorganization can be a primary choice for L-R array multipliers if power is the critical concern. L-R schemes with optimized interconnect achieve the least power consumption in most cases with relatively small delay. When small power-delay product is the main goal, the more complex split array architectures are good candidates.

Paper Details

Date Published: 6 December 2002
PDF: 12 pages
Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.452036
Show Author Affiliations
Zhijun Huang, Univ. of California/Los Angeles (United States)
Milos D. Ercegovac, Univ. of California/Los Angeles (United States)


Published in SPIE Proceedings Vol. 4791:
Advanced Signal Processing Algorithms, Architectures, and Implementations XII
Franklin T. Luk, Editor(s)

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