Share Email Print
cover

Proceedings Paper

Ultra-thin silicon (UTSi(R)) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration
Author(s): Liping Zhang; Alexander A. Sawchuk
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Paper Details

Date Published: 26 December 2001
PDF: 6 pages
Proc. SPIE 4435, Wave Optics and VLSI Photonic Devices for Information Processing, (26 December 2001); doi: 10.1117/12.451150
Show Author Affiliations
Liping Zhang, Univ. of Southern California/Los Angeles (United States)
Alexander A. Sawchuk, Univ. of Southern California/Los Angeles (United States)


Published in SPIE Proceedings Vol. 4435:
Wave Optics and VLSI Photonic Devices for Information Processing
Pierre Ambs; Fred Richard Beyette; Fred Richard Beyette, Editor(s)

© SPIE. Terms of Use
Back to Top