Share Email Print
cover

Proceedings Paper

SDRAM bus schedule of HDTV video decoder
Author(s): Hui Wang; Yan Li He; Lu Yu
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In this paper, a time division multiplexed task scheduling (TDM) is designed for HDTV video decoder is proposed. There are three tasks: to fetch decoded data from SDRAM for displaying (DIS), read the reference data from SDRAM for motion compensating (REF) and write the motion compensated data back to SDRAM (WB) on the bus. The proposed schedule is based on the novel 4 banks interlaced SDRAM storage structure which results in less overhead on read/write time. Two SDRAM of 64M bits (4Bank×512K×32bit) are used. Compared with two banks, the four banks storage strategy read/write data with 45% less time. Therefore the process data rates for those three tasks are reduced. TDM is developed by round robin scheduling and fixed slot allocating. There are both MB slot and task slot. As a result the conflicts on bus are avoided, and the buffer size is reduced 48% compared with the priority bus scheduling. Moreover, there is a compacted bus schedule for the worst case of stuffing owning to the reduced executing time on tasks. The size of buffer is reduced and the control logic is simplified.

Paper Details

Date Published: 20 December 2001
PDF: 8 pages
Proc. SPIE 4674, Media Processors 2002, (20 December 2001); doi: 10.1117/12.451070
Show Author Affiliations
Hui Wang, Zhejiang Univ. (China)
Yan Li He, Zhejiang Univ. (China)
Lu Yu, Zhejiang Univ. (China)


Published in SPIE Proceedings Vol. 4674:
Media Processors 2002
Sethuraman Panchanathan; V. Michael Bove; Subramania I. Sudharsanan, Editor(s)

© SPIE. Terms of Use
Back to Top