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Proceedings Paper

Efficient VLSI implementation of bit plane coder of JPEG 2000
Author(s): Kishore Andra; Tinku Acharya; Chaitali Chakrabarti
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Paper Abstract

To overcome many drawbacks in the current JPEG standard for still image compression, a new standard, JPEG2000, is under development by the International Standard Organization. Embedded bit plane coding is the heart of the JPEG2000 encoder. This encoder is more complex and has significantly higher computational requirements compared to the entropy encoding in current JPEG standard. Because of the inherent bit-wise processing of the entropy encoder in JPEG2000, memory traffic is a substantial component in software implementation. However, in hardware implementation, the lookup tables can be mapped to logic gates and memory accesses for the state bit computation can be reduced significantly by careful design. In this paper, we present an efficient VLSI architecture for embedded bit-plane coding in JPEG2000 that reduces the number of memory accesses. To better understand the interaction of this architecture with the rest of the coder, we also present a system level architecture for efficient implementation of JPEG2000 in hardware.

Paper Details

Date Published: 7 December 2001
PDF: 12 pages
Proc. SPIE 4472, Applications of Digital Image Processing XXIV, (7 December 2001); doi: 10.1117/12.449757
Show Author Affiliations
Kishore Andra, Arizona State Univ. (United States)
Tinku Acharya, Arizona State Univ. and Intel Corp. (United States)
Chaitali Chakrabarti, Arizona State Univ. (United States)


Published in SPIE Proceedings Vol. 4472:
Applications of Digital Image Processing XXIV
Andrew G. Tescher, Editor(s)

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