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Proceedings Paper

Low-power high-speed threshold logic and its application to the design of novel carry lookahead adders
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Paper Abstract

The first main result of this paper is the development of a low power threshold logic gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. The second main result is the development of a novel, low depth, carry look ahead addition scheme. One such adder is also designed using the proposed gate.

Paper Details

Date Published: 21 November 2001
PDF: 8 pages
Proc. SPIE 4591, Electronics and Structures for MEMS II, (21 November 2001); doi: 10.1117/12.449155
Show Author Affiliations
Peter Celinski, Adelaide Univ. (Australia)
Jose Fco. Lopez, Univ. de Las Palmas de Gran Canaria (Spain)
Said F. Al-Sarawi, Adelaide Univ. (Australia)
Derek Abbott, Adelaide Univ. (Australia)


Published in SPIE Proceedings Vol. 4591:
Electronics and Structures for MEMS II
Neil W. Bergmann; Derek Abbott; Alex Hariz; Vijay K. Varadan, Editor(s)

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