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Proceedings Paper

ATM over SDH: design of a STM-16c transceiver using GaAs technology
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Paper Abstract

This paper describes an ATM transceiver implementation with add/drop function over SDH (Synchronous Digital Hierarchy) able to handle STM-16c (OC-48c) signals. The design has been developed using Vitesse HGaAs-IV technology using DCFL (Direct Coupled FET Logic) standard cells and obtaining, in this way, a logic gate level description which could be easily exportable to any technology.

Paper Details

Date Published: 21 November 2001
PDF: 8 pages
Proc. SPIE 4591, Electronics and Structures for MEMS II, (21 November 2001); doi: 10.1117/12.449153
Show Author Affiliations
Oscar Tubio, Univ. de Las Palmas de Gran Canaria (Spain)
Roberto Esper-Chain, Univ. de Las Palmas de Gran Canaria (Spain)
Francisco Gonzalez, Univ. de Las Palmas de Gran Canaria (Spain)
Felix Tobajas, Univ. de Las Palmas de Gran Canaria (Spain)
Valentin de Armas, Univ. de Las Palmas de Gran Canaria (Spain)
Juan A. Montiel-Nelson, Univ. de Las Palmas de Gran Canaria (Spain)
Roberto Sarmiento, Univ. de Las Palmas de Gran Canaria (Spain)


Published in SPIE Proceedings Vol. 4591:
Electronics and Structures for MEMS II
Neil W. Bergmann; Derek Abbott; Alex Hariz; Vijay K. Varadan, Editor(s)

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