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Proceedings Paper

Parameters study to improve sidewall roughness in advanced silicon etch process
Author(s): Hsiang-Chi Liu; Yu-Hsin Lin; Bruce C. S. Chou; Yung-Yu Hsu; Wensyang Hsu
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Paper Abstract

In ICP-RIE process, there have been many investigations on etching rate. However, only few published reports mentioned the sidewall roughness, which is a critical issue for optical devices. Here, experimental investigations about fabrication parameters in the STS Advanced Silicon Etch (ASE) process for sidewall roughness are performed. In our experiments, the photoresist of AZ1500 is used, and several parameters in the ASE process like over time, ramping time, Ar flow rate, platen power, and etching cycle time have been systematically studied. It is found that sidewall mean roughness can be down to 9.11 nm at etching rate of 2.5 micrometers /min. Comparing with other published works at similar sidewall roughness (around 10 nm), our experimental data have the highest etching rate. For the same STS ICP-RIE systems, our data have smallest sidewall roughness, comparing to previous literatures.

Paper Details

Date Published: 21 November 2001
PDF: 11 pages
Proc. SPIE 4592, Device and Process Technologies for MEMS and Microelectronics II, (21 November 2001); doi: 10.1117/12.449008
Show Author Affiliations
Hsiang-Chi Liu, National Chiao Tung Univ. (Taiwan)
Yu-Hsin Lin, National Science Council (Taiwan)
Bruce C. S. Chou, National Science Council (Taiwan)
Yung-Yu Hsu, National Science Council (Taiwan)
Wensyang Hsu, National Chiao Tung Univ. (Taiwan)


Published in SPIE Proceedings Vol. 4592:
Device and Process Technologies for MEMS and Microelectronics II
Jung-Chih Chiao; Lorenzo Faraone; H. Barry Harrison; Andrei M. Shkel, Editor(s)

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