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Proceedings Paper

Submicron high-aspect-ratio silicon beam etch
Author(s): Gary O'Brien; David J. Monk; Khalil Najafi
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Paper Abstract

High aspect ratio beam/trench arrays are etched into silicon substrates using a Surface Technology Systems (STS) deep reactive ion etch (RIE) tool. Process input parameters are varied using high/low values for etch cycle time, passivation cycle time, RF power, and SF6 flow rate. The silicon etch process is characterized using photo-resist masked trench arrays varied from 1.5micrometers through 6micrometers in both width and spacing. A design of experiments (DOE) approach is used to model the following measured outputs: 1) trench depth (R2=0.985), 2) lateral trench etch (R2=0.852), 3) trench sidewall angle (R2=0.815), and 4) aspect ratio dependent etch (R2=0.942), where R2 represents the correlation between actual and model predicted values. The presented characterization models are employed to form beams as small as 300nm wide beams etched to a depth >15micrometers with near vertical sidewalls using standard photolithography equipment. In addition, the provided models are exploited to produce a dual re-entrant/tapered beam etch release process. Released silicon beams are demonstrated over 1200micrometers long and 30micrometers thick with a base width of 300nm.

Paper Details

Date Published: 21 November 2001
PDF: 11 pages
Proc. SPIE 4592, Device and Process Technologies for MEMS and Microelectronics II, (21 November 2001); doi: 10.1117/12.448983
Show Author Affiliations
Gary O'Brien, Univ. of Michigan and Motorola (United States)
David J. Monk, Motorola (United States)
Khalil Najafi, Univ. of Michigan (United States)


Published in SPIE Proceedings Vol. 4592:
Device and Process Technologies for MEMS and Microelectronics II
Jung-Chih Chiao; Lorenzo Faraone; H. Barry Harrison; Andrei M. Shkel, Editor(s)

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