Share Email Print

Proceedings Paper

New architecture of fast parallel multiplier using fast parallel counter with FPA (first partial product addition)
Author(s): Mike Myung-Ok Lee; Byung Lok Cho
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In this paper, we proposed a new First Partial product Addition (FPA) architecture with new compressor (or parallel counter) to CSA tree built in the process of adding partial product for improving speed in the fast parallel multiplier to improve the speed of calculating partial product by about 20% compared with existing parallel counter using full Adder. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14ns of multiplication speed of the 16X16 multiplier is obtained using 0.25um CMOS technology. The architecture of the multiplier is easily opted for pipeline design and demonstrates high speed performance.

Paper Details

Date Published: 19 November 2001
PDF: 11 pages
Proc. SPIE 4593, Design, Characterization, and Packaging for MEMS and Microelectronics II, (19 November 2001); doi: 10.1117/12.448866
Show Author Affiliations
Mike Myung-Ok Lee, Dongshin Univ. (South Korea)
Byung Lok Cho, Sunchon National Univ. (South Korea)

Published in SPIE Proceedings Vol. 4593:
Design, Characterization, and Packaging for MEMS and Microelectronics II
Paul D. Franzon; Ajay P. Malshe; Francis E.H. Tay, Editor(s)

© SPIE. Terms of Use
Back to Top