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Proceedings Paper

Improved heuristics for optimal parallel multiplier synthesis
Author(s): Troy Townsend; Michael Liebelt
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Paper Abstract

Parallel multipliers are of increasing importance for VLSI design, largely driven by the significant increase in demand for computer graphics and digital signal processing. The fastest (and, when pipelined, most area-efficient) multiplier class is partial product reduction tree (PPRT) based multipliers. The previous best known heuristic for PPRT design (published by Stelling et al.) is capable of producing the fastest possible circuits but suffers an infeasible computational burden. This paper introduces some results which significantly reduce the search space of this heuristic. Consequently, the speed of netlist generation is increased, and the circuits generated retain optimal performance. In addition, larger optimal multipliers may be synthesised due to the easing of the computational burden.

Paper Details

Date Published: 19 November 2001
PDF: 11 pages
Proc. SPIE 4593, Design, Characterization, and Packaging for MEMS and Microelectronics II, (19 November 2001); doi: 10.1117/12.448852
Show Author Affiliations
Troy Townsend, Adelaide Univ. (Australia)
Michael Liebelt, Adelaide Univ. (Australia)

Published in SPIE Proceedings Vol. 4593:
Design, Characterization, and Packaging for MEMS and Microelectronics II
Paul D. Franzon; Ajay P. Malshe; Francis E.H. Tay, Editor(s)

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