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Proceedings Paper

Parallel turbo decoder using a low-latency Max-Log-MAP kernel for a VLIW DSP
Author(s): Yingtao Jiang; Jun Ma; Ali Saidi; Yuke Wang
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Paper Abstract

Turbo-Codes have attracted great interest in digital mobile radio due to their remarkable error correcting capabilities. In this paper, we present an optimized Turbo decoder for wireless systems following recommended CDMA2000 standard (192 time frames with 8 states per frame). This decoder is implemented using TI's latest C64x digital signal processor. To achieve the maximum parallelism in TI's VLIW architecture, we have specially redesigned the trellis computation algorithm to improve the decoder throughput and reduce the number of computation operations required. In particular, our proposed algorithm transforms a number of add/subtract operations to multiplication operations. In this way, previously unused functional units become available and therefore, more parallel instructions can run simultaneously, leading to throughput increase and latency reduction. To our findings, current TI's compiler (Code Composer V1.2) fails to generate the optimized assembly code when our algorithms are directly implemented in C. To this end, we have illustrated optimized resource binding and timing schedules by applying code motion and loop transformation techniques. The optimized Turbo decoder can finish one decoding stage in 18.1 microseconds for a C64x DSP running at 400 MHz.

Paper Details

Date Published: 18 October 2001
PDF: 12 pages
Proc. SPIE 4586, Wireless and Mobile Communications, (18 October 2001); doi: 10.1117/12.445228
Show Author Affiliations
Yingtao Jiang, Univ. of Nevada/Las Vegas (United States)
Jun Ma, Broadcom Corp. (United States)
Ali Saidi, Motorola (United States)
Yuke Wang, Univ. of Texas at Dallas (United States)


Published in SPIE Proceedings Vol. 4586:
Wireless and Mobile Communications
Hequan Wu; Jari Vaario, Editor(s)

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