Share Email Print

Proceedings Paper

In-line wafer inspection using 100-megapixel-per-second digital image processing technology
Author(s): Gary Dickerson; Rick P. Wallace
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Reducing defect density to an acceptable level is one of the most challenging problems in manufacturing 16 Mbit DRAMs. To implement an effective defect elimination strategy, it is necessary to have both a defect inspection system that can find all critical defects on the wafer and a strong defect reduction methodology. The optimum system would provide the highest sensitivity along with sufficient inspection speed to fit a majority of inspection applications. This paper describes a new system, the KLA 2110, designed to meet production requirements for speed, sensitivity, and ease of use. The system provides 0.25 micrometers sensitivity with image processing rates 100 times faster than previous generation digital image processing technology.

Paper Details

Date Published: 1 July 1991
PDF: 12 pages
Proc. SPIE 1464, Integrated Circuit Metrology, Inspection, and Process Control V, (1 July 1991); doi: 10.1117/12.44469
Show Author Affiliations
Gary Dickerson, KLA Instruments Corp. (United States)
Rick P. Wallace, KLA Instruments Corp. (United States)

Published in SPIE Proceedings Vol. 1464:
Integrated Circuit Metrology, Inspection, and Process Control V
William H. Arnold, Editor(s)

© SPIE. Terms of Use
Back to Top