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Proceedings Paper

ESD protection design for advanced CMOS
Author(s): Jin Biao Huang; Gewen Wang
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Paper Abstract

ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep- sub-micron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices. The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

Paper Details

Date Published: 15 October 2001
PDF: 9 pages
Proc. SPIE 4600, Advances in Microelectronic Device Technology, (15 October 2001); doi: 10.1117/12.444665
Show Author Affiliations
Jin Biao Huang, YongXin Co. (United States)
Gewen Wang, YongXin Co. (China)

Published in SPIE Proceedings Vol. 4600:
Advances in Microelectronic Device Technology
Qin-Yi Tong; Ulrich M. Goesele, Editor(s)

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