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Proceedings Paper

How small can MOSFETs get?
Author(s): Lothar Risch
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Paper Abstract

Scaling of CMOS technology made possible the key appliances of our information technology society, like the PC, mobile communication, and the internet. Reduction of feature sizes for semiconductor devices continued according to Moore's law for the last 25 years in order to achieve higher integration densities, higher speed, lower power consumption, and lower costs. But now, as we approach the sub 100 nm regime, several roadblocks have been predicted for the next generations down to 35 nm. The latest ITRS roadmap 99 describes in detail the challenges which have to be addressed for the future CMOS technology nodes, regarding lithography, metallization, power dissipation, and circuit design. Also for the MOSFET, performance degradation is a big issue. Because this is not a limitation from basic physical laws, novel architectures for MOSFETs will be needed to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. 25 nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. So, it is very likely that CMOS will not end with today's roadmap at 35 nm or even before, but may continue with non bulk devices and fully depleted channels. Finally, tunnelling from source to drain will set an end to the reduction of channel length, which is estimated to be below 5 nm.

Paper Details

Date Published: 15 October 2001
PDF: 9 pages
Proc. SPIE 4600, Advances in Microelectronic Device Technology, (15 October 2001); doi: 10.1117/12.444664
Show Author Affiliations
Lothar Risch, Infineon Technologies AG (Germany)

Published in SPIE Proceedings Vol. 4600:
Advances in Microelectronic Device Technology
Qin-Yi Tong; Ulrich M. Goesele, Editor(s)

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