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Proceedings Paper

Effects of wafer cooling characteristics after post-exposure bake on critical dimensions
Author(s): Teresa L. Lauck; Masafumi Nomura; Tsutae Omori; Kazutoshi Yoshioka
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Paper Abstract

VLSI design rules require existing LSI design rules to extend to sub-micron and half-micron geometries. Using high resolution resist and 5X stepper (G- line) technology along with a Post-Exposure Bake (PEB) is a common method to improve the resolution. The PEB drives out residual photoresist solvents which can interfere with the develop process, resulting in CD variations. PEB strongly influences CD variations. The authors consider the following PEB parameters in this CD improvement study: (1) altering the PEB temperature, (2) altering the PEB time, and (3) altering the queuing time between PEB and cool prior to develop. The process characterization data includes critical dimension data for 0.8 micrometers lines, including proximity effects data on four high-resolution photoresists.

Paper Details

Date Published: 1 July 1991
PDF: 12 pages
Proc. SPIE 1464, Integrated Circuit Metrology, Inspection, and Process Control V, (1 July 1991); doi: 10.1117/12.44463
Show Author Affiliations
Teresa L. Lauck, Varian Associates (United States)
Masafumi Nomura, Tokyo Electron Ltd. (Japan)
Tsutae Omori, Tokyo Electron Ltd. (Japan)
Kazutoshi Yoshioka, Tokyo Electron Ltd. (Japan)


Published in SPIE Proceedings Vol. 1464:
Integrated Circuit Metrology, Inspection, and Process Control V
William H. Arnold, Editor(s)

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