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Proceedings Paper

10-Gb/s 1:4 demultiplexer in 0.25-um CMOS
Author(s): Lei Tian; Zhigong Wang; Haitao Chen; Tingting Xie; Jianhua Lu; Rui Tao; Yi Dong; Shizhong Xie
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Paper Abstract

This paper described a 1:4 demultiplexer in a standard 0.25 micrometers CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1mm2 area. It consumes 683mW from a 3.3 V supply. The operating bit rates is higher than 10Gb/s.

Paper Details

Date Published: 16 October 2001
PDF: 4 pages
Proc. SPIE 4603, Fiber Optics and Optoelectronics for Network Applications, (16 October 2001); doi: 10.1117/12.444544
Show Author Affiliations
Lei Tian, Southeast Univ. (China)
Zhigong Wang, Southeast Univ. (China)
Haitao Chen, Southeast Univ. (China)
Tingting Xie, Southeast Univ. (China)
Jianhua Lu, Southeast Univ. (China)
Rui Tao, Southeast Univ. (China)
Yi Dong, Tsinghua Univ. (China)
Shizhong Xie, Tsinghua Univ. (China)

Published in SPIE Proceedings Vol. 4603:
Fiber Optics and Optoelectronics for Network Applications
Jian Liu; Zhigong Wang, Editor(s)

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