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Proceedings Paper

Packaging issues using FEA and experimental verification on a Si-based capacitive microrelay
Author(s): C. S. Premachandran; Xiaowu Zhang; T. C. Chai; Victor Samper; T. B. Lim
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Paper Abstract

A Si based capacitive microrelay has been packaged in a premolded package and the packaging issues has been studied and verified by FEA and experimental methods. A quasi-3D finite element modeling has been used to understand the thin cap warpage on the microrelay under different process conditions. Experimental verification on the cap warpage showed that thermal loading is not the only contributing parameter for the cap warpage. A modified model with air loading effect and thermal loading effect validated the experimental result. Solution to overcome this problem has been studied with a hole in the package and reinforcement of cap with epoxy.

Paper Details

Date Published: 2 October 2001
PDF: 8 pages
Proc. SPIE 4558, Reliability, Testing, and Characterization of MEMS/MOEMS, (2 October 2001); doi: 10.1117/12.443005
Show Author Affiliations
C. S. Premachandran, Institute of Microelectronics (Singapore)
Xiaowu Zhang, Institute of Microelectronics (Singapore)
T. C. Chai, Institute of Microelectronics (Singapore)
Victor Samper, Institute of Microelectronics (Singapore)
T. B. Lim, Institute of Microelectronics (Singapore)

Published in SPIE Proceedings Vol. 4558:
Reliability, Testing, and Characterization of MEMS/MOEMS
Rajeshuni Ramesham, Editor(s)

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