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Proceedings Paper

Design of a parallel RISC image processor based on PCI bus
Author(s): Xianyang Jiang; Xubang Shen; Tianxu Zhang
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Paper Abstract

Low-level image processing operations usually involve simple and repetitive operations over the entire input images, thus image processor may communicate with the memory system or each other frequently, hence the image processor would provide high throughput rate. In this article we present an architectural design and analysis of a parallel RISC image processor. The processor was based on PCI bus to speed up a range of image processing operations. The other characteristic of the processor is that a new three-port hostbridge is integrated into the processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed.

Paper Details

Date Published: 20 September 2001
PDF: 5 pages
Proc. SPIE 4555, Neural Network and Distributed Processing, (20 September 2001); doi: 10.1117/12.441675
Show Author Affiliations
Xianyang Jiang, Huazhong Univ. of Science and Technology (China)
Xubang Shen, Huazhong Univ. of Science and Technology (China)
Tianxu Zhang, Huazhong Univ. of Science and Technology (China)

Published in SPIE Proceedings Vol. 4555:
Neural Network and Distributed Processing
Xubang Shen; Jianguo Liu, Editor(s)

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