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Proceedings Paper

Development of a high-performance HWIL missile test facility using standard PC architecture and COTS hardware
Author(s): David J. Shand; Richard Chamberlain; Eric Lord
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Paper Abstract

This paper covers the design & development of a system capable of: (1) Generating IR imagery capable of testing an IR imaging based missile system in a full projection HWIL enviroment. (2) Generating IR imagery and all other signals necessary to test an IR imaging based missile processing unit on the bench. (3) Capturing and analyzing missile outputs allowing full test and debug of the UUT. It aims to show that the recent advances in both PC and Field Programmable Gate Array (FPGA) technology has made such a system technically feasible. It also aims to show that the use of standard PC components and Commercial Off the Shelf (COTS) FPGA boards brings significant benefits to the development of such a system. These benefits include low cost, rapid development, access to a wider technology base and robustness against obsolescence. In particular it shows how the use of FPGA products gives the flexibility in function to allow the design to address its two different goals.

Paper Details

Date Published: 31 August 2001
PDF: 10 pages
Proc. SPIE 4366, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing VI, (31 August 2001); doi: 10.1117/12.438088
Show Author Affiliations
David J. Shand, Matra BAe Dynamics Ltd. (United Kingdom)
Richard Chamberlain, Matra BAe Dynamics Ltd. (United Kingdom)
Eric Lord, Matra BAe Dynamics Ltd. (United Kingdom)


Published in SPIE Proceedings Vol. 4366:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing VI
Robert Lee Murrer, Editor(s)

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