Share Email Print
cover

Proceedings Paper

Sampling strategy and model to measure and compensate overlay errors
Author(s): Chen-Fu Chien; Kuo-Hao Chang; Chih-Ping Chen
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Overlay is one of the key designed rules for producing VLSI devices. In order to have a better resolution and alignment accuracy in lithography process, it is important to model the overlay errors and then to compensate them into tolerances. This study aimed to develop a new model that bridges the gap between the existing theoretical models and the data obtained in real settings and to discuss the overlay sampling strategies with empirical data in a wafer fab. In addition, we used simulation to examine the relations between the various factors and the caused overlay errors. This paper concluded with discussions on further research.

Paper Details

Date Published: 22 August 2001
PDF: 12 pages
Proc. SPIE 4344, Metrology, Inspection, and Process Control for Microlithography XV, (22 August 2001); doi: 10.1117/12.436748
Show Author Affiliations
Chen-Fu Chien, National Tsing Hua Univ. (Taiwan)
Kuo-Hao Chang, National Tsing Hua Univ. (Taiwan)
Chih-Ping Chen, Macronix International Co., Ltd. (Taiwan)


Published in SPIE Proceedings Vol. 4344:
Metrology, Inspection, and Process Control for Microlithography XV
Neal T. Sullivan, Editor(s)

© SPIE. Terms of Use
Back to Top