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Proceedings Paper

Impact and characterization of mask repair on wafer CD uniformity
Author(s): Hsien Min Chang; W. B. Shieh; Johnson Liu; Brian Chu; L. H. Tu; James Cheng; David Wang; Jackie Cheng; Steve L. Hentschel; Vincent Hsu
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Paper Abstract

The performance of an IC device, as we know, depends upon excellent linewidth control in lithography as the geometry of circuits is being decreased. The quality of the mask always plays an important role in this issue. As far as a wafer fab is concerned, the defective mask can lead to not only a dramatic drop in production yield, but also fatal damage for single-chip products. It is observed that a loss of transmission on a mask, detected by a reticle inspection system KLA303-UV STARlight (Simultaneous Transmitted And Reflected light) can bring about unacceptable CD variation on wafers. One major reason for the loss of transmission on masks is from the defect repair process, during which Gallium stain (Ga+) deposits onto the quartz on the chrome side of mask. This problem will become more and more critical for both mask houses and wafer fabs as long as the linewidth keeps shrinking and the design of denser pattern is inevitable. This purpose of this paper is to detail the correlation between wafer CD variation and the relative loss of transmission on the mask. By way of a designed test reticle processed with Gallium deposition by repair tool, inspection, exposure, CD data collection and analysis, we can clearly define the relationship based on I-line mask inspection light source. Following this work, the fab will be able to set up the inspection specifications for any incoming masks to prevent poor CD uniformity occurring in wafers. More importantly, with the design of a variety of patterns with different line/space ratios and device characteristics on this test reticle, we can try to predict the feasibility and severity of the transmission rate loss of mask for 0.15, 0.13 micrometers generations or beyond in order to help mask houses as well as wafer fabs get prepared and work out this problem prior to the advent of the next IC generation.

Paper Details

Date Published: 22 August 2001
PDF: 11 pages
Proc. SPIE 4344, Metrology, Inspection, and Process Control for Microlithography XV, (22 August 2001); doi: 10.1117/12.436741
Show Author Affiliations
Hsien Min Chang, United Microelectronics Corp. (Taiwan)
W. B. Shieh, United Microelectronics Corp. (Taiwan)
Johnson Liu, United Microelectronics Corp. (Taiwan)
Brian Chu, United Microelectronics Corp. (Taiwan)
L. H. Tu, United Microelectronics Corp. (Taiwan)
James Cheng, United Microelectronics Corp. (Taiwan)
David Wang, Precision Semiconductor Mask Corp. (Singapore)
Jackie Cheng, Precision Semiconductor Mask Corp. (Taiwan)
Steve L. Hentschel, KLA-Tencor Corp. (Taiwan)
Vincent Hsu, KLA-Tencor Corp. (Taiwan)

Published in SPIE Proceedings Vol. 4344:
Metrology, Inspection, and Process Control for Microlithography XV
Neal T. Sullivan, Editor(s)

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