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Proceedings Paper

Edge determination for polycrystalline silicon lines on gate oxide
Author(s): John S. Villarrubia; Andras E. Vladar; Jeremiah R. Lowney; Michael T. Postek
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Paper Abstract

In a scanning electron microscope (SEM) top-down secondary electron image, areas within a few tens of nanometers of the line edges are characteristically brighter than the rest of the image. In general, the shape of the secondary electron signal within such edge regions depends upon the energy and spatial distribution of the electron beam and the sample composition, and it is sensitive to small variations in sample geometry. Assigning edge shape and position is done by finding a model sample that is calculated, on the basis of a mathematical model of the instrument-sample interaction, to produce an image equal to the one actually observed. Edge locations, and consequently line widths, are then assigned based upon this model sample. In previous years we have applied this strategy to lines with geometry constrained by preferential etching of single crystal silicon. With this study we test the procedure on polycrystalline silicon lines. Polycrystalline silicon lines fabricated according to usual industrial processes represent a commercially interesting albeit technically more challenging application of this method. With the sample geometry less constrained a priori, a larger set of possible sample geometries must be modeled and tested for a match to the observed line scan, and the possibility of encountering multiple acceptable matches is increased. For this study we have implemented a data analysis procedure that matches measured image line scans to a precomputed library of sample shapes and their corresponding line scans. Linewidth test patterns containing both isolated and dense lines separated form the underlying silicon substrate by a thin gate oxide have been fabricated. Line scans from test pattern images have been fitted to the library of modeled shapes.

Paper Details

Date Published: 22 August 2001
PDF: 10 pages
Proc. SPIE 4344, Metrology, Inspection, and Process Control for Microlithography XV, (22 August 2001); doi: 10.1117/12.436738
Show Author Affiliations
John S. Villarrubia, National Institute of Standards and Technology (United States)
Andras E. Vladar, National Institute of Standards and Technology (United States)
Jeremiah R. Lowney, National Institute of Standards and Technology (United States)
Michael T. Postek, National Institute of Standards and Technology (United States)


Published in SPIE Proceedings Vol. 4344:
Metrology, Inspection, and Process Control for Microlithography XV
Neal T. Sullivan, Editor(s)

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