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Proceedings Paper

Advances in process overlay
Author(s): Paul C. Hinnen; Henry J. L. Megens; Maurits van der Schaar; Richard J. F. van Haren; Evert C. Mos; Sanjay Lalbahadoersing; Frank Bornebroek; David W. Laidler
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Paper Abstract

Advances in wafer processing techniques and the increase of wafer size to 300 mm present new challenges to overlay performance. This paper focuses on advances n the area of process-induced alignment accuracy using the ASML ATHENA alignment system. In the experiments, process variations were deliberately increased to characterize the influence of process-tool settings on wafer alignment performance. In the STI process flow, overlays of <32 nm on marks in silicon or marks in the STI layer have been achieved. In the back-end-of-line, aluminum layers exhibit a significant shift of alignment marks and off-line metrology targets. A geometrical model of the sputter tool is used to explain the origin of this effect. Possible improvements in process corrections are indicated. For the copper dual damascene process investigated here, the dielectrics are non-absorbing. Overlays of 25 nm on marks in silicon and 29 nm on marks in the metal layer are obtained. On 300 mm wafers, a new measurement method is capable of measuring process effects to an accuracy within 6.2 (3(sigma) ). This method is used to measure resist spin effects.

Paper Details

Date Published: 22 August 2001
PDF: 13 pages
Proc. SPIE 4344, Metrology, Inspection, and Process Control for Microlithography XV, (22 August 2001); doi: 10.1117/12.436734
Show Author Affiliations
Paul C. Hinnen, ASML (Netherlands)
Henry J. L. Megens, ASML (Netherlands)
Maurits van der Schaar, ASML (Netherlands)
Richard J. F. van Haren, ASML (Netherlands)
Evert C. Mos, ASML (Netherlands)
Sanjay Lalbahadoersing, ASML (Netherlands)
Frank Bornebroek, ASML (Netherlands)
David W. Laidler, IMEC (Belgium)

Published in SPIE Proceedings Vol. 4344:
Metrology, Inspection, and Process Control for Microlithography XV
Neal T. Sullivan, Editor(s)

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