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Proceedings Paper

Evaluation of overlay measurement target designs for Cu dual-damascene process
Author(s): Moitreyee Mukherjee-Roy; Rakesh Kumar; Ganesh S. Samudra
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Paper Abstract

In this work, different overlay targets were evaluated for the Via first process with conventional USG dielectric. The etch stop layer nitride thickness was limited at 500 A as increasing this thickness will increase the RC delay which is undesirable. A series of targets were evaluated to find out the best performer. Target evaluation was done by their appearance, static repeatability, dynamic repeatability, target correlation, Tool induced shift, Overall misregistration, and residuals. Lot comparisons have also been done using selected targets. Lot average misregistrations (with the best target-2micrometers trench) of 9nm (X + 3(sigma) ), and 15nm (Y + 3(sigma) ) were obtained for the Metal 2 (M2) aligning to Via 1 (V1) level. The different Bar in Bar target structures evaluated were: a. Trench in trench : 1 micrometers and 2 micrometers trenches. b. Wall in wall : 1 micrometers Bars and 2 micrometers Bars. The trench in trench structures were found to work better than bar in bar for conventional dielectric Via first approach. The 2micrometers thick trenches gave the best results for target correlation, dynamic repeatability, and residual values. Metal 1 to metal 2 targets also gave good results and could be used. For low K dielectric and copper integration, a dual hard mask scheme was used. The dual hardmask was used to minimize the interaction of organic dielectric with organic barc and deep UV resist layer as this sometimes gives rise to poisoning issues. For the Organic Low K dielectric and Copper, where the dual hard Mask scheme was followed, the Wall in Wall target gave good contrast and the best results.

Paper Details

Date Published: 22 August 2001
PDF: 11 pages
Proc. SPIE 4344, Metrology, Inspection, and Process Control for Microlithography XV, (22 August 2001); doi: 10.1117/12.436732
Show Author Affiliations
Moitreyee Mukherjee-Roy, Institute of Microelectronics (Singapore)
Rakesh Kumar, Institute of Microelectronics (Singapore)
Ganesh S. Samudra, National Univ. of Singapore (Singapore)

Published in SPIE Proceedings Vol. 4344:
Metrology, Inspection, and Process Control for Microlithography XV
Neal T. Sullivan, Editor(s)

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